1. Field of the Invention
This invention relates to the manufacturing and assembly of large, dense multi-chip electronic packages including large scale integrated circuits, or IC's, and other multi-chip modules, or MCMs, including those used for large microprocessors and other system level, application specific integrated circuits, or ASICs.
2. Description of the Prior Art
The Conventional approach to the fabrication of such large, dense multi-chip electronic packages has been the large or very large scale integrated circuit in which a single large monolithic silicon chip is used as a substrate on which all required circuits are integrated. The chip is then packaged in one of several multi-lead electronic packages.
The complexity of such chips has resulted in relatively costly design cycles and low manufacturing yields. The increasing integration demanded by circuit complexity and high on-chip clock speeds has resulted in the search for alternate packaging approaches.
A substantial improvement for some of the limitations surrounding large scale monolithic IC designs has resulted from the development of multi-chip modules, or MCMs. In a typical MCM, a complex circuit is distributed among two or more separate chips, or sub-chips. Each such sub-chip contains only a portion of the overall circuitry of the MCM and is, therefore, substantially less complex and expensive to design, prototype, build and test than the equivalent monolithic chip.
The challenge for MCMs has been the development of a serviceable multi-chip substrate packaging strategy. There are several attractive high density techniques available for the interface between the multi-chip substrate and the individual sub-chips, including TAB bonding, flip-chips and wire bonding. The effective use of such techniques has been limited by the difficulties and expenses associated with the substrate packaging interface, particularly those resulting from the high thermal management problems caused by the relatively high chip densities achievable with the chip to substrate techniques described above.
What is needed, therefore, is a convenient and economical MCM substrate packaging technique capable of handling sufficient heat dissipation levels, achieving desired higher performance levels and permiting exploitation of the emerging chip to substrate interconnection techniques. Several approaches have been developed which are not completely satisfactory.
One such approach uses silicon wafer substrates in order to achieve an optimum heat transfer between the silicon chips and the substrate. This approach is severely limited by the relative fragility of silicon material as a substrate. This approach requires a high degree of flatness between the non-chip side of the substrate, and the heat sink apparatus used to dissipate the enormous heat generated by the dense chip arrays, in order to avoid breakage of the expensive substrate. This approach does not provide convenient interconnect structures within the silicon and therefore requires sequentially processed thin film structures. This approach does not provide convenient techniques for providing leads or pins for connection out of the silicon substrate.
Aluminum oxide has also been used as an MCM substrate, but it has severe limitations. Aluminum oxide is not closely thermally matched to the silicon chips to be mounted on it and does not have good thermal conductivity. The packaging assemblies using aluminum oxide substrates are also therefore cumbersome, costly and/or ineffective.